1. Field of the Invention
The present invention relates to a semiconductor device and in particular to an effective technology for a semiconductor device having a Silicon On Insulator structure (hereinafter referred to as SOI).
2. Description of the Related Art
At present, a technology referred to as SOI has been used in semiconductor devices in order to achieve lower power consumption and high speed operation. When IC's are manufactured using the SOI technology, they are manufactured from a SOI wafer.
The SOI wafer refers to a wafer having a structure in which a substrate is separated from a semiconductor layer, which servers as an element formation area, by a thick silicon oxide film (hereinafter referred to as the buried oxide film) which is a first insulating film. When a transistor is formed in the semiconductor layer of the SOI wafer, a silicon serving as a channel region and a diffusion region is completely insulated from the substrate by the silicon oxide film.
A transistor formed in the semiconductor layer of the SOI wafer (hereinafter referred to as the SOI transistor) varies in characteristics due to hot carriers which are generated and accumulated in the channel region of the SOI transistor when the SOI transistor is on. In order to suppress such variations, it is necessary to stabilize the operation of the SOI transistor by fixing the potential of the channel region. Since an IC is normally sealed by resin or ceramic, it is difficult to establish electrical connection between the IC and the substrate. Therefore, a technique may be used in which a metal plate is adhered on the bottom surface of the IC so as to provide a bonding that differs from a bonding to the surface of the IC, and fix the potential of the metal plate from the outside of a package.
When the fixing of the potential via the bottom surface of the IC is not carried out, it is necessary to form an electrical contact from the surface of the SOI wafer to the substrate during a wafer process. In the process for a conventional SOI transistor, in order to provide electrical connection between the surface of the wafer and the substrate, a contact hole penetrating the buried oxide film is formed and the hole is filled with a conductive material.
For reference, Japanese Patent Kokai No. 2004-319853, for example, discloses the technique for providing electrical connection between the surface of an IC and a substrate.
However, in the techniques described above and in Japanese Patent Kokai No. 2004-319853, a contact connected to the substrate fixes the potential of the substrate to GND. Accordingly, a terminal connected to GND within the circuit has a connection to the substrate via a wire formed of a first metal. The substrate is vulnerable to an electrical charge due to bias voltage of a stage applied during CVD and etching processes, and bias voltage of an electrostatic chuck used for holding the wafer to the stage. The generated charge is supplied to the transistor via the contact connected to the substrate, causing variations in characteristics of the transistor, deterioration of the gate oxide film, and the like.